1. Field of the Invention
This invention relates to a method for forming pattern data and a method for writing a photomask with additional patterns and in particular to a method for processing data for forming data and writing data for a photomask with additional patterns which make pattern density of photomask uniform, and a method for writing a photomask with additional patterns which makes pattern density of photomask uniform wherein the photomask with additional patterns is used in the producing process of LSI for the main purpose of making the surface of wafer flat in the producing process of LSC.
2. Description of the Prior Art
Recently, it is being required to form a higher quality semiconductor by producing a more flat processing layer on the wafer in the production of the semiconductor, while high integration level and high function level are being required more and more for various LSIs typified by ASIC, due to the tendency toward highly efficient and lighter, thinner and smaller electronic equipment.
As an example in the art of producing a semiconductor having a flat processing layer and insulating layer on the wafer, it is disclosed in U.S. Pat. No. 5,597,668 that a photomask used for the production of the semiconductor is provided with additional patterns above and beyond a wiring pattern.
Herein, the significance of the additional patterns is described referring to FIG. 10. For example, as shown in FIG. 10(a)(i), for a processing layer (wiring layer) having patterns 511 of a high pattern density pattern portion 510 and a low pattern density pattern portion 512, the thickness of the deposited layer (insulating layer) on the processing layers changes largely according to a change in the pattern density, as shown in FIG. 10(a)(ii). As shown in FIG. 10(b)(i), for a processing layer in which pattern density is made uniform by adding additional pattern 531, the thickness of the deposited layer (insulating layer) is made uniform, as shown in FIG. 10(b)(ii), wherein 530 designates additional pattern portions. It should be appreciated that FIG. 10(a)(ii) and FIG. 10(b)(ii) are sectional views showing the concept of the process of production of a semiconductor. FIG. 10(a)(i) and FIG. 10(b)(i) are views taken from the side E1 of FIG. 10(a)(ii) and from the side E2 of FIG. 10(b)(ii), respectively.
In general, it is known that when patterning such a deposited layer or a processing layer which is layered on the deposited layer (and according to the circumstances also the deposited layer), the more flat a deposited layer of the surface of wafer on which a pattern is transferred, the higher the obtained efficiency for transferring the pattern from photomask to wafer. Therefore, forming a processing layer with uniform pattern density enables improved efficiency of transferring the pattern from photomask to wafer.
In general, production of a wafer is finished by repeatedly layering a poly-silicon layer, an insulating layer, a wiring layer and an insulating layer on a wafer in order. However, since the poly-silicon and wiring layers are deposited only on a portion in which patterns exist, which is determined on the basis of design data, the surface of the processed wafer has a varying thickness depending on whether or not patterns exist. Since the insulating layer and the wiring layer are repeatedly layered on the wafer in order, the difference in height between portions in which no pattern exists and portions in which patterns exist gradually increases. As the shapes of patterns on the wafer become minute, the permitted limit of the difference in height narrows.
Further, it is known that when patterning of a photomask is made by means of an electron lithography system, even if data dimensions for patterning of the figures are the same, dimensions of the finished patterns on the photomask differ, depending on the pattern density of the patterns to be formed.
Heretofore, data of additional patterns for producing a photomask capable of generating additional patterns on the processing layer was generated by a method for generating additional patterns as shown in FIG. 11, wherein steps S710 to S740 designate processing steps. Referring to FIG. 12, the state of a wafer at each processing step of FIG. 11 is illustrated.
In step S710 of FIG. 11, areas in which additional patterns are arranged are first determined. In FIG. 12(a), xe2x80x9cdpxe2x80x9d designates wiring patterns included in design data DP. Further, as shown in FIG. 12(b), the minimum interval between wiring patterns and additional patterns is designated as xe2x80x9cdistxe2x80x9d. Figure NA which is over-sized with respect to wiring patterns dp is formed through the sizing figure processing. Area data AD having an area ad in which additional pattern areas are arranged is formed by subtracting the area of figure NA from the area da of the whole of design data DP through the Boolean NOT (FIG. 12(b)).
In step S720 additional patterns are generated in the whole area of FIG. 11. Original arrangement of the additional patterns dt is formed in such a manner that the additional patterns are formed over the entire area ad (FIG. 12(c)), wherein rectangular additional patterns are arranged in the second dimension.
The logical product of area ad in which additional patterns are arranged and arrangement of additional patterns dt is taken, by which arrangement of additional patterns are obtained from the arrangement of additional patterns included in the area ad in which additional patterns are to be arranged (FIG. 12(d), S730)). The arrangement of additional patterns obtained through Boolean AND processing has broken additional patterns and fine additional patterns dd.
In step S740 broken additional patterns dd are eliminated. Since fine figures in the production of a wafer are problematic, the final patterns have an arrangement of additional patterns which does not include broken additional patterns dd, by under-sizing and over-sizing through the sizing figure processing (FIG. 12 (e)). Then, through the Boolean OR, the final pattern data FPO with additional patterns can be obtained from additional pattern data shown in FIG. 12(d) or additional pattern data shown in FIG. 12(e) and original design pattern data DP (FIG. 12(f), S750). Namely, design pattern data dp and additional patterns dt are combined. The pattern data FPO with additional patterns is the data used to produce the photomask.
However, in the production of the photomask, a writing system is generally used in which a positive resist is applied and patterns are written on the positive resist by applying an electron beam or a laser beam to areas in which no pattern data exist.
In the conventional method for generating additional pattern data shown in FIG. 11, design data and additional patterns are formed independently. However, in the above-mentioned writing method using a positive resist, exposure of the design pattern results in writing of the whole additional patterns area so that additional patterns cannot be formed unless the additional patterns are written first. Therefore, in the conventional system for generating additional pattern data mentioned in the description of prior art, additional pattern data are formed independently. Therefore, it is needed to prepare one synthetic pattern data. However, as the design pattern is made more minute, data size of both design pattern data and additional pattern data becomes enormous. It is also necessary to form data having design pattern data and additional data together. Further, time is required for synthesizing of design data and additional data.
In order to simplify the system for generating additional pattern data shown in FIG. 11, an object is restricted only to the wiring layer, wherein the poly-silicon layer, also a deposited layer, is not taken into consideration. In conventional art, additional patterns cannot be generated to the poly-silicon layer. Further, in this system, an area designated for no additional patterns cannot be applied in the wiring layer, even where such is the intention of the designer or where no additional patterns should be present based on the relation of the wiring layer to another design layer.
After generation of additional pattern data, it is necessary to eliminate broken additional patterns or fine additional patterns which are problematic in the production of the wafer. In conventional art, such broken additional patterns or fine patterns are eliminated by under-sizing and over-sizing through the sizing figure processing. However, such additional patterns cannot have hierarchy. Therefore, since the number of figures amounts to anywhere from thousands to hundred millions, the sizing processing takes a great deal of time. Such additional pattern data are processed with a data format called GDSII. As mentioned above, since additional patterns cannot have hierarchy and the number of figures of additional patterns amounts to thousands to hundred millions, the additional patterns alone require some gigabytes of file capacity. Therefore, it takes a great deal of time and labor to handle additional patterns.
As above-mentioned, additional pattern data obtained by the conventional system for generating additional patterns shown in FIG. 11 cannot be applied as a usual writing system for writing patterns by applying an electron beam or a laser beam to parts with no pattern data. Therefore, a solution to this problem is desired. Further, in the system for generating additional pattern data shown in FIG. 11, additional patterns cannot be generated on a poly-silicon layer. Therefore, a solution to this problem is also desired. Further, in the system for generating additional patterns shown in FIG. 11, broken additional patterns or fine additional patterns are eliminated through under-sizing and over-sizing of the sizing figure processing. However, since additional patterns cannot have hierarchy and the number of figures is in the thousands to hundreds of thousands, the sizing processing takes a great deal of hours. Therefore, handling of additional patterns takes much effort.
Accordingly, it is a first object of the present invention to provide a method for forming writing pattern data with additional pattern data for making a photomask having uniform pattern density, wherein this method for forming writing pattern data can be applied not only for wiring layers but also for processing layers, such as a poly-silicon layer, and further wherein it does not take a great deal of time to process data. Further, it is a second object of the present invention to provide a method for writing a photomask with additional patterns having uniform pattern density, wherein this method for writing a photomask with additional patterns can be applied for a writing system in which a positive resist is used and wherein additional patterns can be written by applying an electron beam or a laser beam to parts having no pattern data.
The first object of the present invention is attained by that in designing layout of the electronic circuit or in forming the production data of the photomask, when a minimum interval MI between each figure dp of design pattern data DP which has been designed without consideration to additional patterns and each figure dt of data DT for additional patterns to be formed in a data area is set so as to avoid the interference of each figure dp of the design pattern data DP with each figure dt of data DT for additional patterns to be formed, the following steps are performed. First, the sizing figure processing is taken to the design pattern data DP so that pattern data DP1 having an area NA with no additional pattern is formed by over-sizing each figure dp of pattern data DP by the minimum interval MI, and the Boolean NOT is taken to the design pattern data DP and the pattern data DP1 so as to remove each pattern data DP of the design pattern data DP from the area NA with no additional pattern so that reverse main pattern data MP having reverse patterns mp is formed. The Boolean NOT is then taken to the whole area AA showing the whole area aa of design pattern data area and the pattern data DP1 so as to subtract the area NA of no additional pattern from the whole area aa so that a basic additional pattern area data DA forming a basic additional pattern area da is generated. Next, an area of forbidden additional pattern is determined and the area of the forbidden additional pattern is subtracted from the basic additional pattern area DA so that additional pattern area data FA with additional pattern area fa is formed. Data DT for additional patterns is then generated in which figure dt is placed regularly in the whole area corresponding to the design pattern data area. The Boolean NOT is then taken to the additional pattern area data FA and the data DT for additional patterns so as to remove each figure of data DT for additional patterns from the additional pattern area fa so that reverse additional pattern data FP is formed.
Further, the first object of the present invention is attained for the designing layout of electronic circuit or in forming the production data of the photomask, when a minimum interval MI between each figure dp of design pattern data DP which has been designed without consideration to additional patterns and each figure dt of data DT for additional patterns to be formed in a data area is set so as to avoid the interference of each pattern data DP of the design data pattern data DP with each pattern dt of data DT for additional patterns to be formed, the following is done. The sizing figure processing is first taken to the design pattern data DP so that pattern data DP1 having an area NA with no additional pattern is formed by over-sizing pattern data DP by the minimum MI, and the Boolean NOT is taken to the design pattern data DP and the pattern data DP1 so as to subtract each pattern data DP of the design pattern data DP from the area NA with no additional pattern so that reverse main pattern data MP having reverse patterns mp is formed. The Boolean NOT is then taken to the whole area AA showing the whole area aa of design pattern data area and the pattern data DP1 so as to subtract the area NA of no additional pattern from the whole area aa so that a basic additional pattern area data DA forming a basic additional pattern area da is formed. Next, data DT for additional patterns is generated in which patterns dt forming the basis of the additional patterns area is regularly arranged for the whole area corresponding to the design pattern data area. The Boolean NOT is then taken to the basic additional pattern data DA and the data DT for additional patterns so as to subtract the data DT for additional patterns from the basic additional pattern area da so that reverse additional pattern data FP2 is formed. An area of forbidden additional pattern is then determined and reverse additional pattern data FP is formed by adding the area of forbidden additional pattern to the reverse additional data pattern FP2 through the Boolean OR.
The second object of the present invention is attained by development of a method for writing a uniform pattern density photomask with additional patterns used in the production of LSI in order to make the surface of the process layer(s) of the wafer flat in the production of LSI, the reverse main pattern data MP, reverse additional pattern data FP, the second reverse additional main data GP or the reverse additional pattern data GPi (1xe2x89xa6ixe2x89xa6n) are used directly for photomask writing data or fractured to photomask writing data, respectively, and writings by the respective writing data are made separately so that writing is made on the positive resist applied on a substrate for the photomask for superimposing the writing data.
Herein, the logical operation processing shown in figure data is briefly explained referring to FIG. 9. As shown in FIG. 9(a), a rectangular figure (pattern) A and a rectangular figure (pattern) B are represented in a data area Da. The logical product of the figure A and the figure B, the logical sum of the figure A and the figure B, the reverse of the figure B (also called Inverse or NOT (B) are shown as the shadowed portions in FIG. 9(b), FIG. 9(c), and FIG. 9(d), respectively. As the content of real processing is well-known, this content is omitted herein.
The present invention is a method for processing data for forming writing data for a photomask with additional patterns which photomask is provided with additional patterns so as to make the pattern density of the photomask uniform. The method can be applied for processing layers, such as poly-silicon layers, and others. This method makes it possible to provide a method for forming pattern data without the necessity of expending a great deal of time and the method makes it possible to provide a method for writing a photomask with additional patterns which is applicable for a writing system in which writing of additional patterns is made by applying an electron beam or a laser beam to parts with no pattern data by using a positive resist.
In particular, additional pattern data having an additional pattern generating area with higher freedom and areas of no additional pattern in which any arrangement of additional pattern is prohibited can be formed, wherein in the production of the photomask, it is not needed to combine additional patterns of generated additional pattern data and a pattern of design data so that additional pattern data can be generated with high speed and lower capacity of output.
By such a construction, a method of writing according to the present invention is a method for writing a photomask with additional patterns which photomask is provided with additional patterns so as to make pattern density of the photomask uniform, wherein a positive resist is used, and it makes possible to provide a method of writing wherein the method can be applied for a system in which a positive resist is used and an electron beam or a laser beam is applied to parts having no pattern data, and forming of pattern data for writing is easy.